REDUCED INSTRUCTION

SET COMPUTERS Studies of the execution behavior of high-level language programs have provided guidance in designing a new type of processor architecture：the reduced instruction set computer（RISC）．Assignment statements predominate，suggesting that the simple movement of data should be optimized．There are also many IF and LOOP instructions，which suggest that the underlying sequence control mechanism needs to be optimized to permit efficient pipelining．Studies of operand reference patterns suggest that it should be possible to enhance performance by keeping a moderate number of operands in registers．
These studies have motivated the key characteristics of RISC machines：（1）a limited instruction set with a fixed format．（2）a large number of registers or the use of a compiler that optimizes register usage，and（3）an emphasis on optimizing the instruction pipeline．
The simple instruction set of a RISC lends itself to efficient pipelining because there are fewer and more predictable operations performed per instruction．[1] A RISC instruction set architecture also lends itself to the delayed branch technique，in which branch instructions are rearranged with other instructions to improve pipeline efficiency．
Although RISC systems have been defined and designed in a variety of ways by different groups，the key elements shared by most designs are these：
．A large number of general-purpose registers，or the use of compiler technology to optimize register usage
．A limited and simple instruction set
．An emphasis on optimizing the instruction pipeline
Table 2-1 compares several RISC and non-RISC systems. 1．Instruction Execution Characteristics To understand the line of reasoning of the RISC advocates，we begin with a brief review of instruction execution characteristics．The aspects of computation of interest are as follows：
• Operations performed：These determine the functions to be performed by the processor and its interaction with memory．
• Operands used：The types of operands and the frequency of their use determine the memory organization for storing them and the addressing modes for accessing them．
• Execution sequencing：This determines the control and pipeline organization． 2．The Use of A Large Register File [2] The reason that register storage is indicated is that it is the fastest available storage device，faster than both main memory and cache．The register file is physically small，generally on the same chip as the ALU and control unit，and employs much shorter addresses than addresses for cache and memory．Thus，a strategy is needed that will allow the most frequently accessed operands to be kept in registers and to minimize register-memory operations．
Two basic approaches are possible，one based on software and the other on hardware．The software approach is to rely on the compiler to maximize register usage．The compiler will attempt to allocate registers to those variables that will be used the most in a given time period．This approach requires the use of sophisticated programanalysis algorithms．The hardware approach is simply to use more registers so that more variables can be held in registers for longer periods of time． 3．Characteristics of Reduced Instruction Set Architectures Although a variety of different approaches to reduced instruction set architecture have been taken，certain characteristics are common to all of them．These characteristics are listed in Table 2．1 and described here．
The first characteristic listed in Table 2．1 is that there is one machine instruction per machine cycle．A machine cycle is defined to be the time it takes to fetch two operands from registers，perform an ALU operation，and store the result in a register．Thus，RISC machine instructions should be no more complicated than，and execute about as fast as，microinxtructions on CISC machines．[3] With simple，one –cycle instructions，there is little or no need for microcode；the machine instructions can be hardwired[4]．Such instructions should execute faster than comparable machine instructions on other machines，since it is not necessary to access a microprogram control store during instruction execution．
A second characteristic is that most operations should be register-to-register，with only simple LOAD and STORE operations accessing memory．This design feature simplifies the instruction set and therefore the control unit．For example，a RISC instruction set may include only one or two ADD instructions（e. g. ，integer add，add with carry）；the VAX has 25 different ADD instructions．Another benefit is that such an architecture encourages the optimization of register use，so that frequently accessed operands remain in high-speed storage．
Returning to Table 2-1，a third characteristic is the use of simple addressing modes．Almost all instructions use simple register addressing．Several additional modes，such as displacement and PC-relative，may be included．Other，more complex modes can be synthesized in software from the simple ones．Again，this design feature simplifies the instruction set and the control unit．
A final common characteristic is the use of simple instruction formats．Generally，only one or a few formats are used．Instruction length is fixed and aligned on word boundaries．Field locations，especially the opcode，are fixed．This design feature has a number of benefits．With fixed fields，opcode decoding and register operand accessing can occur simultaneously．Simplified formats simplify the control unit．Instruction fetching is optimized since word-length units are fetched．This also means that a single instruction does not cross page boundaries． NOTES
[1] lend itself to适合于…
[2] register file寄存器组，作为数据或指令的临时存放处的一种多位寄存器组，有时称作栈。
[3] 此句为比较结构no more... than…，中间插入并列句将被比较对象隔开了。
[4] hardwired硬连线的，即机器指令是固化在硬件（芯片）上的。 KEYWORDS
instruction set 指令系统，指令集
reduced instruction set computer（RISC） 精简指令系统计算机
pipeline 流水线
operand 操作数
register 寄存器
compiler 编译器，编译程序
branch instruction 转移指令，分支指令
Complex Instruction Set Computer（CISC） 复杂指令系统计算机
superscalar 超级标量
register file 寄存器组，栈
machine cycle 机器周期
microinstruction 微指令
microcode 微代码，微指令
nncroprogram 微程序
addressing 编址，寻址 精简指令系统计算机（RISC） 对高级语言程序执行性能的研究已经为设计新型处理器体系结构－一精简指令系统计算机提供了指南。赋值语句占据的优势表明应对单纯的数据传送进行优化。还有很多IF和LOOP指令存在，需要优化基本的顺序控制机构，以使流水线作业高效率。操作数引用模式的研究表明，在多个寄存器中保存适当数量的操作数，可以提高性能。
这些研究已经形成了RISC机的一些关键特性：（1）有限的固定格式的指令集；（2）使用大量的寄存器或使用编译器优化寄存器应用；（3）重点优化指令流水线。
因为每条指令完成少数的且多为可预测的操作，RISC的简单指令系统适合高效流水线作业。RISC指令系统体系结构也适合于延迟转移技术，在这种技术中，随同其他指令重新安排转移指令以提高流水线效率。
虽然RISC系统已经由不同的（企业）集团以各种方式进行了定义和设计，但大多数设计所提出的关键元素还是共同的。
 用大量的通用寄存器（或使用编译器技术）来优化寄存器的使用；
 有限的简单指令系统；
 重点优化指令流水线作业。
表2-1比较了几种RISC和非RISC系统。
1．指令执行特性
为了解RISC倡导者们的推理思路，首先观察一下指令执行的一些特性。所要关心的计算特性如下所述。
 所完成的操作：这些操作决定了处理器要完成的功能和处理器与存储器的交互
 所用的操作数：操作数的类型和使用频度决定了存储操作数的存储机制和访问这些操作数的编址方式。
 执行顺序：决定了控制和流水线的机制
2．大寄存器组的应用
使用寄存器存储的理由在于它是可用的最快的存储器件，比主存储器和高速缓存都快。寄存器组实际很小，通常与算术逻辑部件和控制器放在同一芯片上，而且使用比高速缓存和内存储器短很多的地址。因而需要一种允许最频繁访问的操作数保存在寄存器中并使寄存器-存储器操作降至最少的策略。
有两种可以采用的基本方法，一种基于软件，一种基于硬件。软件方法靠编译程序最大限度使用寄存器，编译程序力图将给定时间周期内最常用的那些变量分配到这些寄存器中。这一方法要求使用复杂的程序分析算法。硬件方法就是简单地使用更多的寄存器，使更多的变量保存在寄存器中供长时间使用。
3．精简指令系统体系结构的特性
尽管精简指令系统结构的可用方法有多种，但对它们而言有一些特性是共同的。这些特性列在表2-1中，下面进行解释。
表2-1中列出的第一个特性是每个机器周期有一条机器指令。一个机器周期定义为，机器从寄存器组中取出两个操作数，完成一种算术逻辑部件运算并将结果存入一个寄存器中所用的时间。RISC机器指令应该不比CISC机上的微指令复杂，并且执行起来也很快。因为简单，单周期指令仅需少量或不需要微代码；机器指令可以是硬连线的。这样指令执行起来比其他机器的类似机器指令要快，因为在指令执行期间它不必访问微程序控制存储器。
第二个特性是，大多数操作应该是寄存器对寄存器的，仅有简单的取（LOAD）和存（STORE）操作访问存储器。这种设计特点简化了指令系统，因而也简化了控制器。例如，一个RISC指令系统可以只包括一两种加法（ADD）指令〔例如整数加，进位加〕；VAX机则有25种不同的加法指令。另一好处是这种体系结构促进了对寄存器使用的优化，使得频繁访问的操作数保存在高速存储器中。
从表2-1还可看出第三个特性是采用简单的编址方式。几乎所有指令都采用简单的寄存器编址。几种附加的方式，如移位和与PC有关的方式可以包括进去。另外，更为复杂的方式可以用简单的方式在软件中合成。再次强调，这种设计特点简化了指令系统和控制器。
最后一个共同特性是采用简单的指令格式。一般来讲，只使用了一种或少数几种格式。指令长度是固定的并按字的边界调整。字段的位置，特别是操作码的位置是固定的。这种设计有很多优点，使用固定字段，操作码译码和寄存器操作数访问可同时进行。简化的格式简化了控制器；因为是按字长单位来读取的，所以，取指令也得到优化。这也表明一条指令不会跨页。

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